Patent Number: 8,575,669

Title: Fabricating technique of a highly integrated semiconductor device in which a capacitor is formed between adjacent gate patterns by using a nanotube process

Abstract: The present invention relates to a highly integrated semiconductor device in which a capacitor is formed between adjacent gate patterns by using a nanotube process. A semiconductor memory device according to an example embodiment of the present invention includes a capacitor formed on a first side of a source/drain region positioned between gate patterns of adjacent cell transistors; a plate layer connected to an upper portion of the capacitor, the plate layer being formed in a direction intersecting the gate pattern; and a bit line connected to a second side of the source/drain region of the cell transistor, the bit line being formed in the direction intersecting the gate pattern.

Inventors: Jang; Chi Hwan (Icheon, KR)

Assignee: Hynix Semiconductor Inc

International Classification: H01L 27/08 (20060101); H01L 29/94 (20060101); H01L 21/8242 (20060101)

Expiration Date: 1/05/12017