Patent Number: 8,575,681

Title: Semiconductor memory device and method for manufacturing same

Abstract: A semiconductor memory device includes a substrate, a conductive layer provided on a major surface of the substrate, a stacked body, a memory film, and a channel body. The stacked body includes multiple insulating layers alternately stacked with multiple electrode layers on the conductive layer. The memory film includes a charge storage film provided on side walls of holes made to pierce the stacked body. The channel body includes a pair of columnar portions and a linking portion. The pair of columnar portions is provided on an inner side of the memory film inside the holes. The linking portion is provided inside the conductive layer to link lower ends of the pair of columnar portions. The electrode layers are tilted with respect to the major surface of the substrate. The columnar portions of the channel body and the memory film pierce the tilted portion of the electrode layers.

Inventors: Matsuda; Toru (Mie-ken, JP), Osaki; Tomoya (Mie-ken, JP), Kito; Masaru (Mie-ken, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: H01L 29/792 (20060101)

Expiration Date: 1/05/12017