Patent Number: 8,576,628

Title: Nonvolatile random access memory

Abstract: A nonvolatile random access memory that can be mounted on a substrate during a standard CMOS process. A memory cell comprises: a first MIS transistor including a first semiconductor layer of a first conductivity type in an electrically floating state, first drain and source regions of a second conductivity type formed on the first semiconductor layer, and a first gate electrode formed over the first semiconductor layer via a first gate insulating film; and a second MIS transistor including a second semiconductor layer of the first conductivity type isolated from the first semiconductor layer, second drain and source regions of the second conductivity type formed on the second semiconductor layer, a second gate electrode formed over the second semiconductor layer via a second gate insulating film. The first and second gate electrodes are electrically connected to each other so as to form a floating gate in an electrically floating state.

Inventors: Ueda; Naoki (Osaka, JP)

Assignee: Sharp Kabushiki Kaisha

International Classification: G11C 11/34 (20060101); G11C 16/04 (20060101)

Expiration Date: 1/05/12017