Patent Number: 8,576,649

Title: Sense amplifiers and operations thereof

Abstract: Sense amplifiers and operations thereof are described. More particularly, embodiments of integrated circuit having a sense amplifier coupled to a first bitline and a second bitline of a memory array are described. The sense amplifier generally includes: a latch circuit and a group select input/output circuit, as well as read, reference voltage, and precharge circuitry. Further described is an embodiment of a method for a refresh operation. First data states of a group of memory cells of an array are read and written back as second data states without changing voltages at sense nodes of the latch circuits from the reading, where the second data states are an inverse of the first data states.

Inventors: Nemati; Farid (Redwood City, CA)

Assignee:

International Classification: G11C 7/00 (20060101)

Expiration Date: 1/05/12017