Patent Number:
8,577,950
Title:
Matrix multiplication operations with data pre-conditioning in a high performance computing architecture
Abstract:
Mechanisms for performing matrix multiplication operations with data pre-conditioning in a high performance computing architecture are provided. A vector load operation is performed to load a first vector operand of the matrix multiplication operation to a first target vector register. A load and splat operation is performed to load an element of a second vector operand and replicating the element to each of a plurality of elements of a second target vector register. A multiply add operation is performed on elements of the first target vector register and elements of the second target vector register to generate a partial product of the matrix multiplication operation. The partial product of the matrix multiplication operation is accumulated with other partial products of the matrix multiplication operation.
Inventors:
Eichenberger; Alexandre E. (Chappaqua, NY), Gschwind; Michael K. (Chappaqua, NY), Gunnels; John A. (Yorktown Heights, NY)
Assignee:
International Business Machines Corporation
International Classification:
G06F 7/52 (20060101)
Expiration Date:
1/05/12017