Patent Number: 8,578,226

Title: Apparatus and system for implementing variable speed scan testing

Abstract: In an embodiment of the invention, variable test clock circuitry is provided within an integrated circuit desired to be tested. The variable test clock frequency implements a test clock control register that receives serial test data from a device tester and is configured to serially pass the received test data to scan test chains within the integrated circuit. The test clock control register stores test clock information. The test clock information is provided to a test clock generator where the test clock generator then produces test clock signals at a predetermined frequency. The test clock signal is then provided as a test clock frequency for the scan test chains within the integrated circuit. Methods are also disclosed for operating the variable test clock frequency.

Inventors: Chung; Sung Soo (San Jose, CA)

Assignee: Eigenix

International Classification: G01R 31/28 (20060101)

Expiration Date: 1/05/12017