Patent Number: 8,578,238

Title: ASIP architecture for executing at least two decoding methods

Abstract: A system for execution of a decoding method is disclosed. The system is capable of executing at least two data decoding methods which are different in underlying coding principle, wherein at least one of the data decoding methods requires data shuffling operations on the data. In one aspect, the system includes at least one application specific processor having an instruction set having arithmetic operators excluding multiplication, division and power. The processor is selected for execution of approximations of each of the at least two data decoding methods. The system also includes at least a first memory unit, e.g. background memory, for storing data. The system also includes a transfer unit for transferring data from the first memory unit towards the at least one programmable processor. The transfer unit includes a data shuffler. The system may also include a controller for controlling the data shuffler independent from the processor.

Inventors: Priewasser; Robert (Klagenfurt, AT), Bougard; Bruno (Jodoigne, BE), Naessens; Frederik (Roeselaere, BE)

Assignee: IMEC

International Classification: H03M 13/00 (20060101)

Expiration Date: 1/05/12017