Patent Number: 8,578,304

Title: Implementing mulitple mask lithography timing variation mitigation

Abstract: A method, system and computer program product are provided for implementing multiple mask lithography timing variation mitigation for a multiple mask polysilicon (PC) process. An application specific integrated circuit (ASIC) library includes at least one circuit device for a first mask, and at least one circuit device for a second mask. Critical hold time paths and critical setup time paths are identified in a circuit design. For critical hold time paths, circuit devices in the critical hold time paths are placed on a single mask of either the first mask or the second mask. For critical setup time paths, path delays are reduced by providing a mixture of circuit devices on the first mask and the second mask.

Inventors: Behrends; Derick G. (Rochester, MN), Christensen; Todd A. (Rochester, MN), Hebig; Travis R. (Rochester, MN), Launsbach; Michael (Rochester, MN)

Assignee: International Business Machines Corporation

International Classification: G06F 17/50 (20060101)

Expiration Date: 1/05/12017