Patent Number: 8,578,318

Title: Method for implementing circuit design for integrated circuit and computer readable medium

Abstract: In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.

Inventors: Nomura; Kumiko (Tokyo, JP), Yasuda; Shinichi (Tokyo, JP), Fujita; Shinobu (Inagi, JP), Abe; Keiko (Yokohama, JP), Tanamoto; Tetsufumi (Kawasaki, JP), Ikegami; Kazutaka (Kawasaki, JP), Oda; Masato (Yokohama, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G06F 17/50 (20060101)

Expiration Date: 1/05/12017