Patent Number: 8,713,298

Title: Fast and compact circuit for bus inversion

Abstract: A processor based system with at least one processor, at least one memory controller and optionally other devices having bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.

Inventors: Joshi; Mayur (Dallas, TX)

Assignee: Round Rock Research, LLC

International Classification: G06F 11/00 (20060101); G06F 9/305 (20060101); G06F 13/20 (20060101)

Expiration Date: 4/29/12018