Patent Number: 8,716,072

Title: Hybrid CMOS technology with nanowire devices and double gated planar devices

Abstract: A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.

Inventors: Bangsaruntip; Sarunya (Mount Kisco, NY), Chang; Josephine B. (Mahopac, NY), Chang; Leland (New York, NY), Sleight; Jeffrey W. (Ridgefield, CT)

Assignee: International Business Machines Corporation

International Classification: H01L 29/775 (20060101)

Expiration Date: 5/06/12018