Patent Number: 8,717,066

Title: Clock diagnosis circuit

Abstract: A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.

Inventors: Ohnishi; Naoya (Tokyo, JP), Nakatani; Hiroshi (Tokyo, JP), Sameda; Yoshito (Kanagawa-ken, JP), Takehara; Jun (Tokyo, JP), Toko; Makoto (Saitama-ken, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: H03K 5/22 (20060101)

Expiration Date: 5/06/12018