Patent Number: 8,717,103

Title: Techniques to improve the stress issue in cascode power amplifier design

Abstract: An amplifier includes a first transistor, and a first inductor disposed between the first transistor and a voltage source. A first output node is between the first transistor and the first inductor. The amplifier further includes a second inductor disposed between the first transistor and ground. The amplifier further includes a second transistor, and a third inductor disposed between the second transistor and a ground. A second output node is between the second transistor and the third inductor. The amplifier further includes a fourth inductor disposed between the second transistor and the voltage source. The amplifier further includes a first capacitor disposed between the first output node and the second output node, and a second capacitor disposed between a first mid-node, which is between the first transistor and the first inductor, and a second mid-node, which is between the second transistor and fourth inductor.

Inventors: Leong; Poh Boon (Singapore, SG), Song; Ping (Singapore, SG), Sutardja; Sehat (Los Altos Hills, CA)

Assignee: Marvell World Trade Ltd.

International Classification: H03F 3/04 (20060101)

Expiration Date: 5/06/12018