Patent Number: 8,717,221

Title: Successive approximation register analog-to-digital converter

Abstract: A successive approximation register analog-to-digital converter is provided which includes first and second capacitor arrays configured to generate first and second level voltages, respectively; a comparator configured to compare the first and second level voltages to output a comparison signal; SAR logic configured to generate a digital signal in response to the comparison signal; and a variable common mode selector configured to compare a first analog input voltage and a common mode voltage and to supply one of the first analog input voltage and the common mode voltage to top plates of the first and second capacitor arrays according to a comparison result.

Inventors: Jeon; Young-deuk (Daejeon, KR), Roh; Tae Moon (Daejeon, KR), Kwon; Jong-Kee (Daejeon, KR)

Assignee: Electronics and Telecommunications Research Institute

International Classification: H03M 1/38 (20060101)

Expiration Date: 5/06/12018