Patent Number: 8,717,795

Title: Semiconductor device having plural circuit blocks operating at the same timing

Abstract: Disclosed herein is a device that includes first and second ports arranged in a first direction and first and second circuits arranged between the first and second ports. The first and second ports are coupled to the first and second circuits, respectively. The first and second circuits include first and second sub circuits that control an operation timing thereof based on a timing signal, respectively. The control signal is transmitted through a control line extending in a second direction. Distances between the control line and the first and second sub circuits in the first direction are the same as each other. A coordinate of the control line in the first direction is different from an intermediate coordinate between coordinates of the first and second ports in the first direction.

Inventors: Oishi; Hayato (Tokyo, JP), Nagamine; Hisayuki (Tokyo, JP)

Assignee: Elpida Memory, Inc.

International Classification: G11C 5/02 (20060101)

Expiration Date: 5/06/12018