Patent Number: 8,718,216

Title: Digital phase detector with zero phase offset

Abstract: An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

Inventors: Dreps; Daniel M. (Georgetown, TX), Kim; Kyu-hyoun (Mount Kisco, NY), Wiedemeier; Glen A. (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: H03D 3/24 (20060101)

Expiration Date: 5/06/12018