Patent Number: 8,719,494

Title: Management of partial data segments in dual cache systems

Abstract: For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache. Unrequested data of the whole data segment is split and positioned at a Least Recently Used (LRU) portion of the demotion queue of the higher level of cache. The unrequested data is pinned in place until a write of the whole data segment to the lower level of cache completes.

Inventors: Benhase; Michael T. (Tucson, AZ), Blinick; Stephen L. (Tucson, AZ), Eleftheriou; Evangelos S. (Rueschlikon, CH), Gupta; Lokesh M. (Tucson, AZ), Haas; Robert (Adliswil, CH), Hu; Xiao-Yu (Horgen, CH), Kalos; Matthew J. (Tucson, AZ), Koltsidas; Ioannis (Zurich, CH), Pletka; Roman A. (Uster, CH)

Assignee: International Business Machines Corporation

International Classification: G06F 12/00 (20060101)

Expiration Date: 5/06/12018