Patent Number: 8,719,544

Title: Translated memory protection apparatus for an advanced microprocessor

Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Inventors: Kelly; Edmund J. (San Jose, CA), Cmelik; Robert F. (Sunnyvale, CA), Wing; Malcolm J. (Menlo Park, CA)

Assignee:

International Classification: G06F 12/00 (20060101); G06F 13/00 (20060101)

Expiration Date: 5/06/12018