Patent Number:
8,719,549
Title:
Device to reconfigure multi-level logic networks, method to reconfigure multi-level logic networks, device to modify logic networks, and reconfigurable multi-level logic network
Abstract:
To provide a device to reconfigure multi-level logic networks, which enable logic modification and reconfiguration of a multi-level logic network with small circuit area and low-power dissipation in a simple manner. For example, in the case of reconfiguring a multi-level logic network following logic modification for deleting an output vector F(b) of an objective logic function F(X) corresponding to an input vector b, unmodified pq elements are selected one by one from the nearest pq element E.sub.G to an output side. At this time, among output values of pq elements closer to an input side than selected pq elements, output values corresponding to the input vector, which equal an output value corresponding to any input variable X other than the input vector b are considered modified and thus not selected. Then, a selected output value corresponding to the input vector b is rewritten to an "invalid value".
Inventors:
Sasao; Tsutomu (Iizuka, JP)
Assignee:
Kyushu Institute of Technology
International Classification:
G06F 15/00 (20060101); G06F 15/76 (20060101)
Expiration Date:
5/06/12018