Patent Number: 8,719,638

Title: Assist thread analysis and debug mechanism

Abstract: A processor recognizes a request from a program executing on a first hardware thread to initiate software code on a second hardware thread. In response, the second hardware thread initiates and commences executing the software code. During execution, the software code uses hardware registers of the second hardware thread to store data. Upon termination of the software code, the second hardware thread invokes a hypervisor program, which extracts data from the hardware registers and stores the extracted data in a shared memory area. In turn, a debug routine executes and retrieves the extracted data from the shared memory area.

Inventors: Arndt; Richard Louis (Austin, TX), Frazier; Giles Roger (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 11/00 (20060101)

Expiration Date: 5/06/12018