Patent Number: 8,719,648

Title: Interleaving of memory repair data compression and fuse programming operations in single fusebay architecture

Abstract: An approach for interleaving memory repair data compression and fuse programming operations in a single fusebay architecture is described. In one embodiment, the single fusebay architecture includes a multiple of pages that are used with a partitioning and interleaving approach to handling memory repair data compression and fuse programming operations. In particular, for each page in the single fusebay architecture, a memory repair data compression operation is performed on memory repair data followed by a fuse programming operation performed on the compressed memory repair data.

Inventors: Gorman; Kevin W. (Cambridge, VT), Ouellette; Michael R. (Westford, VT), Ziegerhofer; Michael A. (Jeffersonville, VT)

Assignee: International Business Machines Corporation

International Classification: G11C 29/00 (20060101)

Expiration Date: 5/06/12018