Patent Number: 8,719,746

Title: Reduction of metal fill insertion time in integrated circuit design process

Abstract: Techniques for use in integrated circuit design systems for reducing metal fill insertion time in the integrated circuit design process. In one example, a method includes the following steps. Metal fill data associated with a given layout from a placement and routing database of an integrated circuit design system is stored. The metal fill data is purged from the placement and routing database. At least one change to layout data in the placement and routing database is implemented. The stored metal fill data is loaded into the placement and routing database after the at least one change is implemented to the layout data. A check is performed for an existence of one or more violations associated with the metal fill data due to implementing the at least one change to the layout data in the placement and routing database. A correction procedure is performed on the metal fill data when one or more violations exist.

Inventors: Davidovic; Goran (Munich, DE), Kleeberger; Rupert (Munich, DE), Pugliese; Fulvio (Munich, DE), Inderst; Juergen (Munich, DE)

Assignee: LSI Corporation

International Classification: G06F 9/445 (20060101); G06F 17/50 (20060101)

Expiration Date: 5/06/12018