Patent Number: 8,719,763

Title: Frequency selection with selective voltage binning

Abstract: Approaches for binning integrated circuits using timing are provided. A method includes performing a statistical timing analysis of a design. The method also includes identifying bin sub-spaces within a process space of the design. The method further includes determining a frequency limit for each said bin sub-space. The method additionally includes closing timing to the frequency limit for each said bin sub-space.

Inventors: Bickford; Jeanne P. (Essex Junction, VT), Foreman; Eric A. (Fairfax, VT), Zolotov; Vladimir (Putnam Valley, NY)

Assignee: International Business Machines Corporation

International Classification: G06F 17/50 (20060101); G06F 9/455 (20060101); G06F 11/22 (20060101)

Expiration Date: 5/06/12018