Patent Number: 8,722,478

Title: Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications

Abstract: A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.

Inventors: Jin; Been-Yin (Lake Oswego, OR), Doyle; Brian S (Portland, OR), Kavalieros; Jack T (Portland, OR), Chau; Robert S (Beaverton, OR)

Assignee: Intel Corporation

International Classification: H01L 21/00 (20060101)

Expiration Date: 5/13/12018