Patent Number: 8,743,637

Title: Memory device including redundant memory cell block

Abstract: A clock signal is supplied to a first repair flag flip-flop, a second repair flag flip-flop, a first repair data flip-flop group, and a second repair data flip-flop group to serially transfer a second repair flag and a first repair flag stored in a non-volatile memory to the second repair flag flip-flop and the first repair flag flip-flop. Subsequently, repair data stored in the non-volatile memory is serially output to the first repair data flip-flop group, and repair data of the first repair data flip-flop group and the second repair data flip-flop group is serially transferred.

Inventors: Matsuo; Tatsuru (Kawasaki, JP)

Assignee: Fujitsu Limited

International Classification: G11C 29/00 (20060101)

Expiration Date: 2022-06-03 0:00:00