Patent Number: 8,791,721

Title: Circuit with stacked structure and use thereof

Abstract: A circuit has a stacked structure having at least one symmetric FET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to ground than the asymmetric FET.

Inventors: Anderson; Brent A. (Jericho, VT), Bryant; Andres (Burlington, VT), Nowak; Edward J. (Essex Junction, VT)

Assignee: International Business Machines Corporation

International Classification: H03K 19/20 (20060101)

Expiration Date: 7/29/12018