Patent Number: 8,793,442

Title: Forward progress mechanism for stores in the presence of load contention in a system favoring loads

Abstract: A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.

Inventors: Guthrie; Guy L (Austin, TX), Le; Hien M (Cedar Park, TX), Stuecheli; Jeff A (Austin, TX), Williams; Derek E (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 12/00 (20060101)

Expiration Date: 7/29/12018