Patent Number: 8,793,555

Title: Method of controlling a semiconductor storage device

Abstract: A method of controlling a nonvolatile semiconductor memory includes checking, at a first interval period, an error count of data stored in a first group, the first group including a plurality of blocks/units, and when a first block/unit in the first group satisfies a first condition, assigning the first block/unit to a second group. The method includes checking, at a second interval period, an error count of data stored in the second group, the second interval period being shorter than the first interval period, and when a second block/unit in the second group satisfies a second condition, moving data stored in the second block/unit to an erased block/unit in which stored data is erased among the plurality of blocks/units.

Inventors: Hida; Toshikatsu (Kanagawa, JP), Kanno; Shinichi (Tokyo, JP), Yano; Hirokuni (Tokyo, JP), Kitsunai; Kazuya (Kanagawa, JP), Asano; Shigehiro (Kanagawa, JP), Yano; Junji (Kanagawa, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G11C 29/00 (20060101)

Expiration Date: 7/29/12018