Patent Number: 8,793,628

Title: Method and apparatus of maintaining coherency in the memory subsystem of an electronic system modeled in dual abstractions

Abstract: The present patent document relates to a method and apparatus for maintaining coherency in a memory subsystem of an electronic system modeled in dual abstractions. The portions of the memory subsystem shared between the first abstraction and the second abstraction are shadowed in both abstractions, allowing either abstraction to coherently access memory written by the other. The memory subsystem can also reside solely in a first abstraction, where the second abstraction will synchronize to the first abstraction to access the memory subsystem. Flags associated with memory pages of the memory subsystem are set to indicate which abstraction has most recently updated the memory page. Prior to accessing a memory page, the system will check the flags, copying the contents of the memory in the other abstraction as needed to maintain coherency. The abstractions can operate either synchronously or asynchronously.

Inventors: Varma; Ashutosh (Noida, IN)

Assignee: Cadence Design Systems, Inc.

International Classification: G06F 17/50 (20060101)

Expiration Date: 7/29/12018