Patent Number: 8,793,630

Title: Clock tree planning for an ASIC

Abstract: The present invention discloses a method and system for clock tree planning for an ASIC, the method comprising: determining a netlist and a timing constraint file of the ASIC; creating a sequential device undirected graph for sequential devices in the netlist according to connection relationships of the sequential devices in the netlist and timing constraint relationships of the sequential devices in the timing constraint file; grouping the sequential devices in the netlist according to the sequential device undirected graph, such that the sequential devices in one group do not have a timing constraint relationship with the sequential devices in another group. The ASIC design method improved by using this method will reduce the design cycle from weeks to days, and enable designer to quickly plan the clock tree, thus reducing the design time and improving the design efficiency.

Inventors: Ge; Liang (Shanghai, CN), Pu; Suoming (Shanghai, CN), Xu; Chen (Beijing, CN), Yu; Bo (Beijing, CN)

Assignee: International Business Machines Corporation

International Classification: G06F 17/50 (20060101)

Expiration Date: 7/29/12018