Patent Number: 8,793,632

Title: Techniques for electromigration stress determination in interconnects of an integrated circuit

Abstract: In one or more embodiments, one or more methods, processes, and/or systems described can determine stress failures in interconnect segments of integrated circuit designs and correct those failure via modifying the interconnect segments of the integrated circuit designs with one or more additions to the interconnect segments of the integrated circuit designs. Potentials can be received from a simulation, and one or more failures of an interconnect segment can be determined via the potentials from the simulation. For example, a failure can be determined via a comparison with a potential from the simulation and a critical potential. An interconnect segment can be modified with a stub such that a comparison with a potential from the simulation and a critical potential to provide a non-failing, modified interconnect segment.

Inventors: Demircan; Ertugrul (Austin, TX), Shroff; Mehul D. (Austin, TX)

Assignee: Freescale Semiconductor, Inc.

International Classification: G06F 17/50 (20060101)

Expiration Date: 7/29/12018