Patent Number: 8,793,644

Title: Display and automatic improvement of timing and area in a network-on-chip

Abstract: A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way.

Inventors: Michel; Daniel (Rungis, FR), Van Ruymbeke; Xavier (Issy les Moulineaux, FR), Godet; Pascal (Jouy en Josas, FR), Leloup; Xavier (Santa Clara, CA)

Assignee: Qualcomm Technologies, Inc.

International Classification: G06F 17/50 (20060101)

Expiration Date: 7/29/12018