Patent Number: 8,796,073

Title: Low cost die-to-wafer alignment/bond for 3d IC stacking

Abstract: The cost associated with alignment in a stacked IC device can be reduced by aligning multiple die instead of a single die during the alignment step. In one embodiment, the alignment structures are placed in the scribe line instead of within the die itself. Aligning four die instead of one eliminates the need for as many alignment indicators and thus more silicon on the wafer can be used for active areas. In addition, this method allows for yield improvement through binning of dies having the same yield configuration.

Inventors: Gu; Shiqun (San Diego, CA), Toms; Thomas R. (Dripping Springs, TX)

Assignee: QUALCOMM Incorporated

International Classification: H01L 21/00 (20060101)

Expiration Date: 8/05/12018