Patent Number: 8,796,099

Title: Inducing channel strain via encapsulated silicide formation

Abstract: Methods of forming semiconductor structures having channel regions strained by encapsulated silicide formation. Embodiments include forming a transistor, depositing an interlevel dielectric (ILD) layer above the transistor, forming contact recesses exposing portions of source/drain regions of the transistor, forming metal-rich silicide layers on the exposed portions of the source/drain regions, forming metal contacts in the contact recesses above the metal-rich silicide layers, and converting the metal-rich silicide layer to a silicon-rich silicide layer. In other embodiments, the metal-rich silicide layers are formed on the source/drain regions prior to ILD layer deposition. Embodiments further include forming a transistor, depositing an ILD layer above the transistor, forming contact recesses exposing portions of source/drain regions of the transistor, forming metal liners in the contact recesses, forming metal fills in the contact recesses, and forming silicide layers on the source/drain regions by reacting portions of the metal liners with portions of the source/drain regions.

Inventors: Alptekin; Emre (Wappingers Falls, NY), Ozcan; Ahmet S. (Pleasantville, NY), Sardesai; Viraj Y. (Poughkeepsie, NY), Tran; Cung D. (Newburgh, NY)

Assignee: International Business Machines Corporation

International Classification: H01L 21/336 (20060101)

Expiration Date: 8/05/12018