Patent Number: 8,796,735

Title: Fabrication of a vertical heterojunction tunnel-FET

Abstract: Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.

Inventors: Lauer; Isaac (Mahopac, NY), Majumdar; Amlan (White Plains, NY), Solomon; Paul M. (Yorktown Heights, NY), Koester; Steven J. (Ossining, NY)

Assignee: International Business Machines Corporation

International Classification: H01L 29/66 (20060101); H01L 21/336 (20060101)

Expiration Date: 8/05/12018