Patent Number: 8,796,839

Title: Semiconductor package including a power plane and a ground plane

Abstract: An apparatus that comprises a power ground/arrangement that comprises a first semiconductor die configured as a central processing unit (CPU). The power/ground arrangement further comprises a first metal layer that provides only one of (i) a power signal and (ii) a ground signal, and a second metal layer that provides the other one of (i) the power signal and (ii) the ground signal. The apparatus further comprises a second semiconductor die configured as a memory that is coupled to the power/ground arrangement. The second semiconductor die is configured to receive power signals and ground signals from the power/ground arrangement. The second semiconductor die is further configured to provide signals to the CPU via the power/ground arrangement and to receive signals from the CPU via the power/ground arrangement. The second semiconductor die is coupled to the power/ground arrangement only along a single side of the second semiconductor die.

Inventors: Sutardja; Sehat (Los Altos Hills, CA), Wu; Albert (Palo Alto, CA)

Assignee: Marvell International Ltd.

International Classification: H01L 23/04 (20060101)

Expiration Date: 8/05/12018