Patent Number: 8,796,868

Title: Semiconductor layout

Abstract: Apparatuses and methods for an improved semiconductor layout are described herein. Embodiments of the present invention provide a microelectronic device including a microelectronic die and one or more redistribution paths formed thereon for electrically interconnecting at least one bond pad with an exposed portion of the redistribution path. The redistribution paths, bond pads, and exposed portions may be configured to result in the device having a width narrowed by at least the width of the bond pads due to their absence on at least one edge.

Inventors: Ngo; Thomas (San Jose, CA), Liou; Shiann-Ming (Campbell, CA)

Assignee: Marvell International Ltd.

International Classification: H01L 23/48 (20060101); H01L 23/52 (20060101); H01L 23/495 (20060101)

Expiration Date: 8/05/12018