Patent Number: 8,797,053

Title: Positioning and socketing for semiconductor dice

Abstract: Devices and methods useful for testing bare and packaged semiconductor dice are provided. As integrated circuit chips become smaller and increasingly complex, the interface presented by a chip for connectivity with power supplies and other components of the system into which it is integrated similarly becomes smaller and more complex. Embodiments of the invention provide micron-scale accuracy alignment capabilities for fine pitch device first level interconnect areas. Embodiments of the invention employ air-bearings to effectuate the movement and alignment of a device under test with a testing interface. Additionally, testing interfaces comprising membranes supported by thermal fluids are provided.

Inventors: Rutigliano; Michael L. (Chandler, AZ), Moret; Eric J. M. (Beaverton, OR), Shia; David (Hillsboro, OR)

Assignee: Intel Corporation

International Classification: G01R 31/00 (20060101)

Expiration Date: 8/05/12018