Patent Number: 8,797,075

Title: Low power oversampling with reduced-architecture delay locked loop

Abstract: In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.

Inventors: Yang; Wei-Lien (Phoenix, AZ)

Assignee: Intel Corporation

International Classification: H03L 7/06 (20060101)

Expiration Date: 8/05/12018