Patent Number: 8,797,076

Title: Duty ratio correction circuit, double-edged device, and method of correcting duty ratio

Abstract: A duty ratio correction circuit, includes: a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal; phase interpolator configured to generate a fourth clock signal and a fifth clock signal based on phase interpolation of any two of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or a second inverted signal that is obtained by inverting the third clock signal; and a multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal.

Inventors: Kibune; Masaya (Machida, JP)

Assignee: Fujitsu Limited

International Classification: H03K 3/017 (20060101)

Expiration Date: 8/05/12018