Patent Number: 8,797,077

Title: Master-slave flip-flop circuit

Abstract: A master-slave flip-flop circuit includes: a master circuit to receive input data in a first state of a reference clock and hold the input data in a second state of the reference clock to output intermediary data; and a slave circuit to receive the intermediary data in the second state and hold the intermediary data in the first state to output data, wherein the master circuit includes: a feedback two-input NOR gate to receive an output of the master circuit and a first clock; an input three-input NOR gate to receive the input data, a second clock, and a third clock; and a synthesis two-input NOR gate to receive an output of the input three-input NOR gate and an output of the feedback two-input NOR gate.

Inventors: Sasagawa; Ryuhei (Koto, JP)

Assignee: Fujitsu Limited

International Classification: H03K 3/289 (20060101)

Expiration Date: 8/05/12018