Patent Number: 8,815,669

Title: Metal gate structures for CMOS transistor devices having reduced parasitic capacitance

Abstract: A method of forming a field effect transistor (FET) device includes forming a gate structure over a substrate, the gate structure including a wide bottom portion and a narrow portion formed on top of the bottom portion; the wide bottom portion comprising a metal material and having a first width that corresponds substantially to a transistor channel length, and the narrow portion also including a metal material having a second width smaller than the first width.

Inventors: Cai; Jin (Cortlandt Manor, NY), Pei; Chengwen (Danbury, CT), Robison; Robert R. (Colchester, VT), Wang; Ping-Chuan (Hopewell Junction, NY)

Assignee: International Business Machines Corporation

International Classification: H01L 21/336 (20060101)

Expiration Date: 8/26/12018