Patent Number: 8,815,718

Title: Vertical surround gate formation compatible with CMOS integration

Abstract: A method for fabricating vertical surround gates in a semiconductor device array structure such that the processes are compatible with CMOS fabrication. The array structure includes a CMOS region and an array region. The method includes forming a polish stop layer, a plurality of patterning layers, a CMOS layer over a substrate, array pillars and array trenches. Forming the array pillars and trenches includes removing the CMOS cover layer and patterning layers. The method further includes doping portions of the substrate within the array trenches. The method includes forming vertical surround gates in the array trenches, an array filler layer to fill in the array trenches, and a CMOS photoresist pattern over the array filler layer. The method includes etching the CMOS trenches down through a portion of the substrate, such that the array pillars under the shared trench are etched to form contact holes.

Inventors: Lam; Chung H. (Peekskill, NY), Li; Jing (Ossining, NY)

Assignee: International Business Machines Corporation

International Classification: H01L 21/28 (20060101); H01L 21/336 (20060101)

Expiration Date: 8/26/12018