Patent Number: 8,815,733

Title: Isolated wire structures with reduced stress, methods of manufacturing and design structures

Abstract: An integrated circuit (IC) including a set of isolated wire structures disposed within a layer of the IC, methods of manufacturing the same and design structures are disclosed. The method includes forming adjacent wiring structures on a same level, with a space therebetween. The method further includes forming a capping layer over the adjacent wiring structures on the same level, including on a surface of a material between the adjacent wiring structures. The method further includes forming a photosensitive material over the capping layer. The method further includes forming an opening in the photosensitive material between the adjacent wiring structures to expose the capping layer. The method further includes removing the exposed capping layer.

Inventors: Gambino; Jeffrey P. (Westford, VT), He; Zhong-Xiang (Essex Junction, VT), Lee; Tom C. (Essex Junction, VT)

Assignee: International Business Machines Corporation

International Classification: H01L 21/4763 (20060101)

Expiration Date: 8/26/12018