Patent Number: 8,816,433

Title: Checkerboarded high-voltage vertical transistor layout

Abstract: In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.

Inventors: Parthasarathy; Vijay (Mountain View, CA), Banerjee; Sujit (San Jose, CA), Manley; Martin H. (Saratoga, CA)

Assignee: Power Integrations, Inc.

International Classification: H01L 29/66 (20060101)

Expiration Date: 8/26/12018