Patent Number: 8,819,323

Title: Data transfer circuit and data transfer method

Abstract: A port A request queue is configured with a port AQ0 to a port AQn for each of request types Q0 to Qn connected with a requester resource busy flag controller Q0 to a requester resource busy flag controller Qn, respectively. A port A resource checking unit of a port X arbiter unit gives instructions to the requester resource busy flag controller of the port AQ0 to turn a busy flag on when it is determined that a data request from the port AQ0 has difficulty in being output to a port X inter-port arbiter unit due to resources being busy as a result of referring to a resource information unit of a port X resource managing unit. The port AQ0 inhibits output of a data request as long as the busy flag is on.

Inventors: Nishiyashiki; Masaru (Kawasaki, JP)

Assignee: Fujitsu Limited

International Classification: G06F 13/14 (20060101)

Expiration Date: 8/26/12018