Patent Number: 8,819,342

Title: Methods and apparatus for managing page crossing instructions with different cacheability

Abstract: An instruction in an instruction cache line having a first portion that is cacheable, a second portion that is from a page that is non-cacheable, and crosses a cache line is prevented from executing from the instruction cache. An attribute associated with the non-cacheable second portion is tracked separately from the attributes of the rest of the instructions in the cache line. If the page crossing instruction is reached for execution, the page crossing instruction and instructions following are flushed and a non-cacheable request is made to memory for at least the second portion. Once the second portion is received, the whole page crossing instruction is reconstructed from the first portion saved in the previous fetch group. The page crossing instruction or portion thereof is returned with the proper attribute for a non-cached fetched instruction and the reconstructed instruction can be executed without being cached.

Inventors: DeBruyne; Leslie Mark (Cary, NC), Dieffenderfer; James Norris (Apex, NC), Mcilvaine; Michael Scott (Raleigh, NC), Stempel; Brian Michael (Raleigh, NC)

Assignee: QUALCOMM Incorporated

International Classification: G06F 12/08 (20060101)

Expiration Date: 8/26/12018