Patent Number: 8,819,391

Title: Memory controller with enhanced block management techniques

Abstract: Methods and apparatuses for managing unusable blocks in a memory module are provided. The memory table may include a plurality of unusable block addresses in the memory module where the plurality of unusable block addresses is arranged in a sequential order in the memory table. A number of unusable blocks in the memory module is identified by reading a word that represents the number of unusable blocks from the memory table. A first pair of addresses comprises a first unusable block address and a first corresponding mapped memory address. The pair of addresses are read from the memory table and stored in a storage element of a controller. Only a single pair of addresses is stored in the storage element of the controller at any one time according to one embodiment.

Inventors: Lock; Lai Khuan (Georgetown, MY), Hew; Yin Chong (Selama, MY)

Assignee: Altera Corporation

International Classification: G06F 12/10 (20060101)

Expiration Date: 8/26/12018