Patent Number: 8,819,508

Title: Scan test circuitry configured to prevent violation of multiplexer select signal constraints during scan testing

Abstract: An integrated circuit comprises a decoder having a plurality of select signal outputs, a multiplexer having a plurality of select signal inputs subject to a specified select signal constraint, and scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells coupled between respective ones of the select signal outputs of the decoder and respective ones of the select signal inputs of the multiplexer. The scan test circuitry is configured to control at least a given one of the scan cells so as to prevent violation of the select signal constraint in conjunction with scan testing. The multiplexer may be, for example, a one-hot multiplexer for which the select signal constraint indicates that only one of the select signal inputs should receive a logic high select signal at a particular time.

Inventors: Devta Prasanna; Narendra B. (San Jose, CA), Tekumalla; Ramesh C. (Breinigsville, PA)

Assignee: LSI Corporation

International Classification: G01R 31/28 (20060101)

Expiration Date: 8/26/12018