Patent Number: 8,819,607

Title: Method and apparatus to minimize clock tree skew in ICs

Abstract: A method and circuit with minimized clock skews in an IC. One embodiment includes placing an application specific IP block at a predetermined location in an integrated circuit (IC), the IC having a clock network that distributes a clock signal, the clock network having one or more clock buses, each clock bus providing the clock signal to a row of logic blocks of the IC, each clock bus having one or more clock nets; determining the electrical load on a first clock driver driving a first clock net of a first clock bus providing the clock signal to a first row of logic blocks; identifying at least one other target clock driver to be coupled to the first clock net, the at least one other target clock driver driving a clock net of a clock bus providing the clock signal to a row of logic blocks other than the first row of logic blocks; selecting the at least one other target clock driver to couple to the first clock net; coupling the at least one other target clock driver to the first clock net; and verifying by one or more types of simulation the desired functional and timing performance of the affected logic blocks after connection of the compatible clock nets.

Inventors: Pan; Philip (Fremont, CA), Lin; Yen-Fu (San Jose, CA), Yu; Ling (Cupertino, CA), Mal; Prosenjit (Fremont, CA)

Assignee: Altera Corporation

International Classification: G06F 17/50 (20060101)

Expiration Date: 8/26/12018